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LT3745-1 1 37451f typical application description 16-channel 50ma led driver with buck controller the lt ? 3745-1 integrates a 16-channel led driver with a 55v buck controller. the led driver lights up to 75ma/36v of leds in series per channel, and the buck controller gen- erates an adaptive bus voltage supplying the parallel led strings. each channel has individual 6-bit dot correction current adjustment and 12-bit grayscale pwm dimming. both dot correction and grayscale are accessible via a serial data interface in lvds logic. a 4% led current match- ing and a 0.5s minimum led on-time can be achieved at 50ma per channel. the LT3745-1 performs full diagnostic and protection against open/short led and overtemperature fault. the fault status is sent back through the serial data interface . the 30mhz fully-buffered, cascadable lvds serial data interface makes the chip extremely suitable for large screen lcd dynamic backlighting and mono-, multi-, full-color led displays. the lt3745 uses a ttl /cmos serial data interface instead of lvds. 16-channel led driver, 1mhz buck, 10 leds, 25ma to 75ma per channel, 500hz 12-bit dimming features applications n 6v to 55v power input voltage range n 16 independent led outputs up to 75ma/36v n 4% led current matching at 50ma ( typ 1%) n 6-bit dot correction current adjustment n 12-bit grayscale pwm dimming n 0.5s minimum led on- time n adaptive led bus voltage for high efficiency n cascadable 30mhz lvds serial data interface n full diagnostic and protection: individual open/short led and overtemperature fault n 40- lead 6mm 6mm qfn package n large screen display led backlighting n mono-, multi-, full-color led displays n led billboards and signboards l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 8058810 lvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . en/uvlo sync rt ss v cc i set t set scki + scki ? sdi + sdi ? ldi scko + scko ? sdo + sdo ? led13 led14 led15 led00 led01 led02 . . . . . . LT3745-1 100k v in 42v to 55v en v cc 3v to 3.6v v in cap 0.47f gate gnd fb isp isn 4.7f 267k 10k 47f 2 47h 25m pwmck + pwmck ? lvds 2.048mhz lvds clock 37451 ta01 10f 46.4k 10nf 60.4k 32.4k www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 2 37451f absolute maximum ratings v in .......................................................................... 57 v cap ......................................................... v in C 8 v to v in gate .............................................................. cap to v in led 00 to led 15, isp , isn ......................................... 40 v isp ................................................. isn C 1 v to isn + 1 v fb , rt , t set , i set ....................................................... 2 v v cc ............................................................... C0.3 v to 4 v scki + , scki C , scko + , scko C , sdi + , sdi C , sdo + , sdo C , ldi , pwmck + , pwmck C , sync , ss , en / uvlo ............................................. C0.3 v to v cc operating junction temperature range ( notes 2, 3) lt 3745 e -1 ......................................... C40 c to 125 c lt 3745 i -1 .......................................... C40 c to 125 c storage temperature range .................. C65 c to 125 c (note 1) electrical characteristics symbol parameter conditions min typ max units supply v in v in operating voltage l 6 55 v i vin v in supply current v en/uvlo = 0v no switching 0.2 0.4 2 0.55 a ma v cc v cc operating voltage l 3 3.6 v i vcc v cc supply current (note 4) v en/uvlo = 0v led channel off, 30mhz data off led channel on, 30mhz data off led channel on, 30mhz data on 0.25 11 16 19 ma ma ma ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, v cc = 3.3v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 0v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , unless otherwise noted. order information lead free finish tape and reel part marking* package description temperature range lt3745euj-1#pbf lt3745euj-1#trpbf lt3745uj-1 40-lead (6mm 6mm) plastic qfn C40c to 125c lt3745iuj-1#pbf lt3745iuj-1#trpbf lt3745uj-1 40-lead (6mm 6mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pin configuration 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 en/uvlo led07 led06 led05 led04 led03 led02 led01 led00 scki ? sync led08 led09 led10 led11 led12 led13 led14 led15 scko ? i set t set v in gate cap isp isn fb ss rt scki + sdi ? sdi + ldi v cc pwmck + pwmck ? sdo + sdo ? scko + 21 30 10 1 t jmax = 125c, ja = 34c/w, jc = 2.5c/w exposed pad (pin 41) is gnd, must be soldered to pcb www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 3 37451f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, v cc = 3.3v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 0v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , unless otherwise noted. symbol parameter conditions min typ max units undervoltage lockout (uvlo) v cc uvlo threshold v cc rising v cc falling 2.76 2.58 2.86 2.68 2.96 2.78 v v en/uvlo shutdown threshold uvlo threshold i vcc <1ma v en/uvlo rising v en/uvlo falling 0.35 1.26 1.18 1.30 1.22 1.34 1.26 v v v i en/uvlo en/uvlo bias current v en/uvlo = v cc = 3.3v 0.1 1 a (v in C v cap ) uvlo threshold (v in C v cap ) rising (v in C v cap ) falling 4.6 4.2 4.9 4.5 5.2 4.8 v v soft-start (ss) i ss soft-start charge current v ss = 1v C16 C12 C8 a soft-start discharge current v ss = v cc , v en/uvlo = 1v 330 a v ss(th) soft-start reset threshold 0.35 v oscillator v rt rt pin voltage 1.186 1.205 1.224 v i rt rt pin current limit v rt = 0v C80 a f osc oscillator frequency r t = 280k r t = 105k r t = 46.4k 184 460 935 204 510 1035 224 560 1135 khz khz khz f sync sync frequency range (note 5) r t = 348k 200 1000 khz sync logic high level voltage low level voltage v cc = 3v to 3.6v 2.4 0 v cc 0.6 v v error amplifiers and loop dynamics v fb fb regulation voltage v isn = 5v l 1.186 1.210 1.234 v i fb fb input bias current v isn = 5v, v fb regulated C120 na led regulation voltage v isn = 5v, v fb = 1v 0.6 0.7 0.8 v t off(min) minimum gate off- time v isp = v isn = 5v, v fb = 1v 120 ns t on(min) minimum gate on- time ( v isp C v isn ) = 60mv, v isn = 5v , v fb = 1v 200 ns current sense amplifier isp/isn pin common mode v isp = v isn l 0 36 v v in to isn dropout voltage (v in C v isn ) v isp = v isn , v fb = 1v l 1.7 2.1 v current limit sense threshold ( v isp C v isn ) v fb = 1v 30 44 58 mv i isp isp input bias current C24 a i isn isn input bias current C48 a gate driver v bias cap bias voltage (v in C v cap ) 7v < v in < 55v 6.4 6.8 7.1 v i cap cap bias current limit (v in C v cap ) = v bias C 0.5v 22 ma gate high level (v in C v gate ) i gate = C100ma 0.4 v gate low level (v gate C v cap ) i gate = 100ma 0.3 v gate rise time c gate = 3.3nf to v in 30 ns gate fall time c gate = 3.3nf to v in 30 ns www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 4 37451f symbol parameter conditions min typ max units led driver v iset trimmed i set pin voltage l 1.181 1.205 1.229 v ledxx operating voltage v in = 48v, v isp = v isn = v ledxx l 36 v ledxx leakage current led channel off, v in = 48v, v isp = v isn = 36v, v ledxx = 24v 0.2 a i led led constant sink current v isp = v isn = 5v, v ledxx = 1v reg dc = 0x00 reg dc = 0x20 reg dc = 0x3f l l l 23.3 47.5 70 25.3 50.5 74 27.3 53.5 78 ma ma ma ?i ledc current mismatch between channels v isp = v isn = 5v, v ledxx = 1v, reg dc = 0x20 (note 6) l 1 4 % ?i ledd current mismatch between devices v isp = v isn = 5v, v ledxx = 1v, reg dc = 0x20 (note 7) l 1 3 % ?i line led current line regulation v isp = v isn = 5v, v ledxx = 1v, reg dc = 0x 20, v cc = 3v to 3.6v (note 8) 0.1 0.2 %/v ?i load led current load regulation v isp = v isn = 5v, reg dc = 0x20, v ledxx = 1v to 3v (note 9) 0.1 0.2 %/v v open open led threshold v isp = v isn = 5v, v ledxx falling 0.35 v v sht short led threshold v isp = v isn = 5v, v ledxx rising 3.7 3.9 4.1 v t ledon minimum led on- time v isp = v isn = 5v, reg gs = 0x001 0.5 s thermal protection i tset t set output current v tset = 1v l 19.0 19.8 20.6 a t set over temperature threshold t a = 25c 510 mv serial data interface v sih v sil single-ended input (note 10) high level voltage low level voltage v cc = 3v to 3.6v 2.4 0 v cc 0.6 v v i si single-ended input current v cc = 3v to 3.6v, si = v cc or gnd C0.2 0.2 a v cm v dth v dtl differential input (note 11) common mode high threshold low threshold v cc = 3v to 3.6v v id = 200mv v cm = 1.2v v cm = 1.2v 0.1 C100 50 C50 2.3 100 v mv mv i di differential input current v cc = 3.6v; di + , di C = 2.4v or 0v C0.2 0.2 a v od differential output voltage (note 11) r l = 100 230 330 430 mv ?v od v od magnitude change between complementary outputs r l = 100 1 10 mv v os differential output offset voltage r l = 100 1.1 1.2 1.3 v ?v os v os magnitude change between complementary outputs r l = 100 1 10 mv i osd differential output short- circuit current do + = 0v or do C = 0v C6 C8 ma electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, v cc = 3.3v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 0v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , unless otherwise noted. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 5 37451f timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, v cc = 3v to 3.6v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 5v, v ledxx = 1v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , c scko + /scko C = c sdo + /sdo C = 15pf, unless otherwise noted. symbol parameter conditions min typ max units f scki data shift clock frequency l 30 mhz f pwmck pwmck clock frequency l 25 mhz t wh-cki t wl-cki scki pulse duration scki = h (figure 3) scki = l (figure 3) l l 16 16 ns ns t wh- pwm t wl- pwm pwmck pulse duration pwmck = h (figure 4) pwmck = l (figure 4) l l 20 20 ns ns t wh-ldi ldi pulse duration ldi = h (figure 3) l 20 ns t su-sdi sdi-scki setup time sdi C scki (figure 3) l 5 ns t hd-sdi scki-sdi hold time scki C sdi (figure 3) l 5 ns t su-ldi scki-ldi setup time scki C ldi (figure 3) l 5 ns t hd-ldi ldi-scki hold time ldi C scki (figure 3) l 15 ns t pd-sck scki-scko propagation delay (rising) scki C scko (figure 3) l 33 50 ns t pd-sck scki-scko propagation delay (falling) scki C scko (figure 3) l 33 50 ns ?t pd-sck sck duty cycle change ?t pd-sck = t pd-sck C t pd-sck 0 ns t pd-sd scko-sdo propagation delay scko C sdo (figure 3) l 2 5 8 ns t pd- pwm pwmck -led propagation delay pwmck C i led (figure 4) 55 ns t r-so scko/sdo rise time c load = 15pf, 10% to 90% 2.6 ns t f-so scko/sdo fall time c load = 15pf, 90% to 10% 2.6 ns table 1. test parameter equations ? i ledc (%) = i outmax(0 ? 15) C i outmin(0 ? 15) 2 ? i outavg(0 ? 15) ? 100 (1) ? i ledd (%) = i outavg(0 ? 15) C i outcal i outcal ? 100 (2) i outcal = 2500 ? 1.205v r iset ? ? ? ? ? ? (3) ? i line (% / v) = i outn v cc = 3.6v C i outn v cc = 3v i outn v cc = 3v ? 100 0.6v (4) ? i load (% / v) = i outn v outn = 3v C i outn v outn = 1v i outn v outn = 1v ? 100 2v (5) v id = v(di + )? v(di ? ) (6) v cm = v(di + ) + v(di ? ) 2 (7) v od = v(do + )? v(do ? ) (8) v os = v(do + ) + v(do ? ) 2 (9) www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 6 37451f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3745e-1 is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3745i-1 is guaranteed over the full C40c to 125c operating junction temperature range. note 3: this ic includes thermal shutdown protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when thermal shutdown protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: the v cc supply current with led channel on highly depends on the led current setting and ledxx pin voltage; its test condition is r iset = 60.4k, reg dc = 0x3f, reg gs = 0xfff, v isp = v isn = 5v, v ledxx = 1v. the v cc supply current with serial data interface on highly depends on v cc supply voltage, scki + /scki C clock frequency, scko + /scko C , sdo + /sdo C loading capacitance, and pwmck + / pwmck C clock frequency; its test condition is v cc = 3.3v, f scki + /scki C = 30mhz, c scko + /scko C = c sdo + /sdo C = 15pf, f pwmck + / pwmck C = 409.6khz. electrical characteristics note 5: the sync frequency must be higher than the rt programmed oscillator frequency, and is suggested to be around 20% higher. any sync frequency higher than the suggested value may introduce sub-harmonic oscillation in the converter due to insufficient slope compensation . see application information section. note 6: the current mismatch between channels is calculated as equation?1 in table 1. note 7: the current mismatch between devices is calculated as equations?2 and 3 in table 1. note 8: the led current line regulation is calculated as equation 4 in table 1. note 9: the led current load regulation is calculated as equation 5 in table 1. note 10: the specifications of single-ended input si apply to the ldi pin . note 11: the specifications of differential inputs di + /di C apply to scki + / scki C , sdi + /sdi C and pwmck + / pwmck C ; the specifications of differential outputs do + /do C apply to scko + /scko C and sdo + /sdo C . the parameters v id , v cm , v od and v os are defined in equations 6 to 9 and measured in the parameter test setup. c l r l do + do ? 37451 pt c l d parameter test setup www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 7 37451f typical performance characteristics 200hz 2-level dc dimming 200hz 4-level dc dimming adaptive led bus voltage i adaptive led bus voltage ii adaptive led bus voltage iii adaptive led bus voltage iv 100hz 8:1 gs dimming 100hz 4096:1 gs dimming 500hz 4096:1 gs dimming t a = 25c, unless otherwise noted. circuit of figure 7: dc 15 = 020 gs 15 = 0200 v pwmck 0.5v/div v led15 2v/div v out 2v/div i led15 50ma/div 5ms/div 37451 g01 circuit of figure 7: dc 15 = 020 gs 15 = 0001 v pwmck 0.5v/div v led15 2v/div v out 2v/div i led15 50ma/div 500ns/div 37451 g02 circuit of figure 7: dc 15 = 020 gs 15 = 0001 v pwmck 0.5v/div v led15 2v/div v out 2v/div i led15 50ma/div 500ns/div 37451 g03 circuit of figure 7: (a) en = 1, gs 15 = 0fff (c) en = 1, dc 15 = 000 (b) en = 1, dc 15 = 03f v scki 0.5v/div v led15 2v/div v out 2v/div i led15 50ma/div 1ms/div 37451 g04 (a) (b) (c) (a) (b) (c) circuit of figure 7: (a) en = 0, gs 15 = 0fff (c) en = 1, dc 15 = 000 (b) en = 1, dc 15 = 03f (d) en = 1, dc 15 = 020 v scki 0.5v/div v led15 2v/div v out 2v/div i led15 50ma/div 0.5ms/div 37451 g05 (a) (b) (c) (d) circuit of figure 7: dc 00-15 = 03f , gs 00-15 = 0fff i l 0.5a/div v out 0.5v/div 2ms/div 37451 g06 circuit of figure 7: dc 00-15 = 020 , gs 00-15 = 0800 i l 0.5a/div v out 0.5v/div 2ms/div 37451 g07 circuit of figure 7: dc 00-15 = 03f , gs 00-01 = 01ff , gs 02-03 = 03ff, gs 04-05 = 05ff , gs 06-07 = 07ff , gs 08-09 = 09ff, gs 10-11 = 0bff , gs 12-13 = 0dff , gs 14-15 = 0fff i l 0.5a/div v out 0.5v/div 2ms/div 37451 g08 circuit of figure 7: dc 00-03 = 03f , gs 00-03 = 03ff , dc 04-07 = 02f, gs 04-07 = 07ff , dc 08-11 = 01f , gs 08-11 = 0bff, dc 12-15 = 00f , gs 12-15 = 0fff i l 0.5a/div v out 0.5v/div 2ms/div 37451 g09 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 8 37451f typical performance characteristics i vcc vs v cc C shutdown mode i vcc vs v cc C channel off, data off v cc uvlo threshold vs temperature en/uvlo uvlo threshold vs temperature (v in -v cap ) uvlo threshold vs temperature oscillator frequency f osc vs r t buck efficiency shutdown i vin vs v in quiescent i vin vs v in t a = 25c, unless otherwise noted. 0 60 65 efficiency (%) 70 80 75 90 85 100 95 0.1 0.2 0.3 load current (a) 0.4 37451 g10 0.5 0.6 0.7 0.8 0.9 1.0 48v in , 4v out at 200khz 24v in , 12v out at 1mhz 12v in , 4v out at 500khz 0 0 i vin (a) 1 3 2 4 5 10 20 v in (v) 37451 g11 30 40 50 60 t = 25c t = 125c t = ?40c 0 0.38 i vin (ma) 0.39 0.41 0.40 0.42 0.43 10 20 v in (v) 37451 g12 30 40 50 60 t = 25c t = 125c t = ?40c v cc (v) 3.0 0 i vcc (a) 100 200 300 400 500 3.1 3.2 3.3 3.4 37451 g13 3.5 3.6 t = 125c t = ?40c t = 25c v cc (v) 3.0 10.0 i vcc (ma) 10.5 11.0 11.5 12.0 3.1 3.2 3.3 3.4 37451 g14 3.5 3.6 t = 125c t = ?40c t = 25c ?50 2.60 v cc (v) 2.75 2.70 2.65 2.80 2.85 2.90 ?25 25 50 75 100 125 0 junction temperature (c) 37451 g15 uvlo ? uvlo + ?50 1.20 v en/uvlo (v) 1.26 1.24 1.22 1.28 1.30 1.32 ?25 25 50 75 100 125 0 junction temperature (c) 37451 g16 uvlo ? uvlo + ?50 4.40 v in - v cap (v) 4.60 4.50 4.70 4.80 4.90 ?25 25 50 75 100 125 0 junction temperature (c) 37451 g17 uvlo ? uvlo + 20 60 100 180 220 260 0 f osc (khz) 400 200 600 800 1000 140 300 r t (k) 37451 g18 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 9 37451f typical performance characteristics fb regulation voltage vs load current led regulation voltage vs load current soft-start charge current i ss vs temperature current sense threshold vs v isn cap bias voltage (v in -v cap ) vs v in cap bias voltage (v in -v cap ) vs i cap v iset pin voltage vs temperature oscillator frequency f osc vs temperature t a = 25c, unless otherwise noted. junction temperature (c) ?50 480 f osc (khz) 490 500 510 520 ?25 0 25 37451 g19 50 75 100 125 load current (ma) 0 1.204 v fb (v) 1.206 1.208 1.210 1.212 1.216 200 400 600 800 37451 g20 1000 1200 1.214 load current (ma) 0 0.60 v led (v) 0.62 0.64 0.66 0.68 0.72 200 400 600 800 37451 g21 1000 1200 0.70 ?50 ?11.0 i ss (a) ?10.8 ?10.6 ?10.4 ?10.0 ?10.2 ?25 0 25 50 75 100 125 junction temperature (c) 37451 g22 v isn (v) 0 35 v isp ? v isn (mv) 40 45 50 55 60 10 20 30 37451 g23 40 t = 125c t = ?40c t = 25c 0 6.70 v in -v cap (v) 6.74 6.78 6.90 6.86 6.82 10 20 30 40 50 60 v in (v) 37451 g24 t = 25c t = 125c t = ?40c 0 6.20 v in -v cap (v) 6.30 6.40 6.90 6.80 6.70 6.60 6.50 4 8 12 16 2420 i cap (ma) 37451 g25 t = 25c t = 125c t = ?40c ?50 1.200 v iset (v) 1.202 1.210 1.208 1.206 1.204 ?25 0 25 50 75 100 125 junction temperature (c) 37451 g26 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 10 37451f typical performance characteristics short led threshold vs v isn t set current vs i set current t set threshold vs temperature led current derating vs temperature led current vs dot correction led current i led vs led voltage v led led current variation i led vs temperature t a = 25c, unless otherwise noted. nominal led current vs r iset 37451 g27 40 0 i led (ma) 10 50 40 30 20 80 120 160 200 240 280 320 r iset (k) 81 0 i led (ma) 10 80 70 60 50 40 30 20 16 24 32 40 48 56 64 dot correction +1 37451 g28 0 10 80 70 60 50 40 30 20 0 i led (ma) 0.5 1.0 1.5 2.0 2.5 3.0 v led (v) 37451 g29 dc = 03f dc = 020 dc = 000 junction temperature (c) ?50 49.0 i led (ma) 49.5 50.0 50.5 51.0 ?25 0 25 50 75 100 125 37451 g30 0 0 v led (v) 30 18 24 12 6 8 16 24 32 40 v isn (v) 37451 g31 0 0 i tset (a) 20 12 16 8 4 4 8 12 16 20 i iset (a) 37451 g32 ?50 350 450 400 v tset (mv) 700 600 650 550 500 ?25 0 25 50 125 75 100 junction temperature (c) 37451 g33 80 0 10 i led (ma) 60 40 50 30 20 85 90 95 100 120 105 110 115 junction temperature (c) 37451 g34 ot = 0 ot = 1 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 11 37451f pin functions en/ uvlo ( pin 1): enable and undervoltage lockout (uvlo) pin. the pin can accept a digital input signal to enable or disable the chip. tie to 0.35v or lower to shut down the chip or tie to 1.34v or higher for normal op- eration. this pin can also be connected to v in through a resistor divider to program a power input uvlo threshold. if both the enable and uvlo functions are not used, tie this pin to v cc pin. led00 to led15 (pins 2 to 9, 22 to 29): led driver output pins. connect the cathodes of led strings to these pins. scki ? , scki + (pins 10, 11): serial interface lvds logic clock input pins. sdi ? , sdi + (pins 12, 13): serial interface lvds logic data input pins. ldi (pin 14): serial interface ttl /cmos logic latch input pin. an asynchronous input signal at this pin latches the serial data in the shift registers into the proper registers and the status information is ready to shift out with the coming clock pulses. see more details in the operation section. v cc ( pin 15): logic and control supply pin. the pin powers serial data interface and internal control circuitry . must be locally bypassed with a capacitor to ground. pwmck + , pwmck ? ( pins 16, 17): grayscale pwm dimming lvds logic clock input pins. individual pwm dimming signal is generated by counting this clock pulse from zero to the bits in its 12-bit grayscale pwm register. sdo + , sdo ? (pins 18, 19): serial interface lvds logic data output pins. scko + , scko ? (pins 20, 21): serial interface lvds logic clock output pins. sync (pin 30): switching frequency synchronization pin. synchronizes the internal oscillator frequency to an exter - nal clock applied to the sync pin. the sync pin is ttl / cmos logic compatible. tie to ground or v cc if not used. rt (pin 31): timing resistor pin. programs the switching frequency from 200khz to 1mhz. see table 2 for the rec- ommended r t values for common switching frequencies. ss (pin 32): soft-start pin. placing a capacitor here pro- grams soft-start timing to limit inductor inrush current during start-up. the soft-start cycle will not begin until all the v cc , en/uvlo, and (v in -v cap ) voltages are higher than their respective uvlo thresholds. fb (pin 33): feedback pin. the pin is regulated to the internal bang-gap reference 1.210v during start-up and precharging phases. connect to a resistor divider from the buck converter output to program the maximum led bus voltage. see more details in the applications information section. isn (pin 34): negative inductor current sense pin. the pin is connected to one terminal of the external inductor current sensing resistor and the buck converter output supplying parallel led channels. isp (pin 35): positive inductor current sense pin. the pin is connected to the inductor and the other terminal of the external inductor current sensing resistor. cap (pin 36): v in referenced regulator supply capacitor pin. the pin holds the negative terminal of an internal v in referenced 6.8 v linear regulator used to bias the gate driver circuitry . must be locally bypassed with a capacitor to v in . gate (pin 37): gate driver pin. the pin drives an external p-channel power mosfet with a typical peak current of 1a . connect this pin to the gate of the power mosfet with a short and wide pcb trace to minimize trace inductance. v in (pin 38): power input supply pin. must be locally bypassed with a capacitor to ground. t set (pin 39): temperature threshold setting pin. a resistor to ground programs overtemperature threshold. see more details in the applications information section. i set (pin 40): nominal led current setting pin . a resistor to ground programs the nominal led current for all the channels. see more details in the applications informa- tion section. gnd (exposed pad pin 41): ground pin. must be soldered to a continuous copper ground plane to reduce die tem- perature and to increase the power capability of the device. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 12 37451f block diagram 32 35 34 30 31 1 15 33 16 14 c ss c vcc r fb2 r fb1 v cc v cc ss isn rt isp sync 12a en/uvlo fb pwmck + sdi + sdi ? 17 pwmck ? ldi ot status info (fault led xx ) x scki prechg v ss < 1v (v in -v cap ) v in v in c in r s m1 l d1 gate cap 6.8v 1.205v i set t set v ptat i ref ot uv 1.210v + ? reference bias and uvlo ramp osc s r q + ? + ? + ? r t driver g m 1 + ? 37 38 36 c cap c out v out pg por g m 2 0.7v led00 led01 led15 en + ? ? . . . ? c0 shift register c1 192 192 16x 16x fs fs sdi scko sdo fs en gs register dc register 12-bit pwm dimming constant current sink 6-bit dot correction open/short led 12 12 en 6 6 fault led xx pwmck i ref led xx gnd 37451 bd 40 39 + ? + ? r iset r tset s r q 12 13 scki + scki ? 10 11 20 21 scko + scko ? 18 19 41 sdo + sdo ? www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 13 37451f operation the lt3745 -1 integrates a single constant - frequency current-mode nonsynchronous buck controller with six- teen linear current sinks. the buck controller generates an adaptive output led bus voltage to supply parallel led strings and the sixteen linear current sinks regulate and modulate individual led strings. its operation is best understood by referring to the block diagram. start-up the LT3745-1 enters shutdown mode when the en/ uvlo pin is lower than 0.35v. once the en/uvlo pin is above 0.35v, the part starts to wake up internal bias currents, generate various references , and charge the capacitor c cap towards 6.8v regulation voltage . this v in referenced voltage regulator (v in C v cap ) will supply the internal gate driver circuitry driving an external p-channel mosfet in normal operation. the LT3745-1 remains in undervoltage lockout (uvlo) mode as long as any one of the en/uvlo, v cc , and (v in C v cap ) uvlo flags is high. their uvlo thresholds are typically 1.30v, 2.86v, and 4.9v, respectively. after all the uvlo flags are cleared, the buck controller starts to switch, and the soft-start ss pin is released and charged by a 12a current source , thereby smoothly ramping up the inductor current and the output led bus voltage. power-on-reset (por) during start-up, an internal power-on-reset (por) high signal blocks the input signals to the serial data interface and resets all the internal registers except the 194-bit shift register. the 1-bit frame select (fs) register, 1-bit enable led channel ( en) register , individual 12-bit grayscale ( gs) registers , and individual 6-bit dot correction ( dc) registers are all reset to zero . thus all the led channels are turned off initially with the default grayscale (0x000) and dot correc- tion (0x00) setting. once the part completes its soft-start (i.e., the ss pin voltage is higher than 1v) and the output led bus voltage is power good (i.e., within 5% of its fb programmed regulation level), the por signal goes low to allow the input signals to the serial data interface . any fault triggering the soft-start will generate another por high signal and reset internal registers again. lvds serial data interface the LT3745-1 has a 30mhz, fully-buffered, cascadable lvds ( low voltage differential signals) serial data in- terface . due to the differential signal transmission and the low voltage swing, lvds delivers the benefits of low noise generation, high noise rejection, and low power consumption for high data rate signals. therefore, the LT3745-1 uses lvds logic for scki + , scki ? , sdi + , sdi ? , scko + , scko ? , and sdo + , sdo ? signals (high data rate signals), and ttl /cmos logic for ldi signal (low data rate signal). in this data sheet, the differential signals scki + , scki ? , sdi + , sdi ? , scko + , scko ? and sdo + , sdo ? are abbreviated to scki, sdi, scko and sdo, respectively. the LT3745-1 can be connected to microcontrollers, digital signal processors (dsps), or field programmable gate arrays (fpgas) in two different topologies shown in figure 1. in topology #1, the ldi signal needs global routing while the scki, and sdi signals only need local routing between chips. each chip provides the scko sig- nal along with the sdo signal to drive the next chip. the skew inside the chip between the scki and sdi signals is balanced internally. the skew outside the chip between the scko and sdo signals can be easily balanced by parallel routing these two pairs of signals between chips. the sdi signal is received with the scki signal, and the sdo signal is sent with the scko signal. in a low data rate application with a small number of cascaded chips, the topology ?#1 can be simplified to the topology #2 by ignoring the scko outputs. figure 2 shows two serial data input sdi frames (gs frame and dc frame ) and one serial data output sdo frame ( status frame). all the frames have the same 194- bit in length and are transmitted with the msb first and the lsb last . the sdi frames are sent with the scki signal and the sdo frame is received with the scko signal. the c0 bit (frame select) determines any sdi frame to be either a gs frame (c0 = 0) or a dc frame (c0 = 1), and the c1 bit (en) enables (c1 = 1) or disables (c1 = 0) all the led channels. the status frame reads back the t set pin resistor-programmable over- temperature flag and individual open/short led fault flags, as well as the individual 6-bit dc setting. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 14 37451f operation inside the part, there are one 194- bit shift register sr[0:193], one 1-bit frame select (fs) register, one 1-bit enable led channel (en) register, sixteen 12-bit grayscale (gs) registers, sixteen 6-bit dot correction (dc) registers, one 1-bit over temperature (ot) flag register, and sixteen 1-bit led fault flag registers. the input of the 194-bit shift register, i.e., the input of the first bit sr[0], is connected to the sdi signal. the output of the 194-bit shift register, i.e., the output of the last bit sr[193] is connected to the sdo signal. the scki signal shifts the sdi frame (gs or dc frame) in and the scko signal shift the sdo frame (status frame) out of the 194-bit shift register with their rising edges. the ldi high signal latches the sdi frame (gs or dc frame) from the 194-bit shift register into correspond- ing fs, en, gs or dc registers, and loads the sdo frame (status frame) from the ot and led fault flag registers to the 194-bit shift register at the same time. therefore, a daisy-chain type loop communication with simultaneous writing and reading capability is implemented. figure 3 illustrates the timing relation among serial input and serial output signals in more detail. one dc frame fol- lowed by another gs frame is sent through the ldi, scki, and sdi signals. at the same time, two status frames are received through the scko and sdo signals. the rising edges of the scki signal shift a frame of 194-bit data at 100 100 scko + ldo controller chip 1 scko ? sdo + sdo ? 100 sdi ? sdi + 100 scki ? scki + ldi scko + scko ? sdo + sdo ? scki + ldi sck- ? sdi + sdi ? 100 100 chip 2 LT3745-1 lvds topology #1 scko + scko ? sdo + sdo ? scki + ldi sck- ? sdi + sdi ? 100 100 chip n scko + scko ? sdo + sdo ? scki + ldi sck- ? sdi + sdi ? 100 scko + ldo controller chip 1 scko ? sdo + sdo ? 100 sdi ? sdi + 100 scki ? scki + ldi scko + scko ? sdo + sdo ? scki + ldi sck- ? sdi + sdi ? 100 chip 2 LT3745-1 lvds topology #2 scko + scko ? sdo + sdo ? scki + ldi sck- ? sdi + sdi ? 100 chip n scko + scko ? sdo + sdo ? 37451 f01 scki + ldi sck- ? sdi + sdi ? figure 1. tw o topologies of the LT3745-1 lvds serial data interface www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 15 37451f figure 2. serial data frame format operation figure 3. serial data input and output timing chart command register: c1: enable led channels - enable = 1, disable = 0 c0: frame select - gs frame = 0, dc frame = 1 status register: s0-s15: led 0-15 fault - fault = 1, ok = 0 f0: ot - over temperature = 1, ok = 0 194 bits gs frame gs 0, 12 bits dc 0, 6 bits dc 15, 6 bits dc 0, 6 bits dc 15, 6 bits 37451 f02 gs 15, 12 bits lsb lsb lsb lsb lsb lsb msb msb msb msb msb msb c0c1 dc frame c0c1 x x x x x x s0 0 0 0 0 0 s15 0 0 0 0 0 x x x x x x status frame f00 37451 f03 scki 186 1 186 input data status data 193 1 193 192 194 194 193 192 193 194 1 c0 = 0 c0 = 1 c1 c0 = 1 f0 c1 0 x f0 c1 c1 gs 0 lsb c0 = 0 f0 c1 gs 0 lsb gs 15 msb gs 15 msb c1 f0 0 gs 0 lsb gs 0 lsb + 1 gs 15 msb gs 15 msb dc 0 lsb dc 0 lsb dc 0 lsb + 1 dc 15 msb dc 15 msb 194 1 1 sdi ldi sr[1] sr[0] scko sdo/ s r[38 5] t wh-ldi t hd-ldi t su-ldi t wh-cki t wl-cki t su-sdi t hd-sdi t pd-sck t pd-sck t pd-sd dc 15 msb dc 15 msb dc 15 msb ? 1 gs 15 msb dc 15 msb f0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 16 37451f operation the sdi pins into the 194-bit shift register sr[0:193]. after 194 clock cycles, all the 194-bit data sit in the right place waiting for the ldi signal. an asynchronous ldi high signal latches the 1-bit fs register, 1-bit en register, and individual 12-bit gs registers (when fs = 0) or 6-bit dc registers (when fs = 1) for each channel. at the same time, a frame of status information, including over temperature flag and individual open/short led fault flags, is parallel loaded into the 194-bit shift register and will be shifted out with the coming clock cycles. constant current sink each led channel has a local constant current sink regu- lating its own led current independent of the led bus voltage v out . the recommended led pin voltage ranges from 0.8v to 3v. as shown in the typical performance characteristics i led vs v led curves , the led current i led has the best load regulation when the led pin voltage v led sits above 0.5v. a lower led bus voltage v out may not regulate all the led channels across temperature, current, and manufacturing variation, while a higher led bus voltage v out will force a higher led pin voltage across the current sink, thereby dissipating more power inside the part. see more details about the choice of the led bus voltage and the power dissipation calculation in the application information section. dot correction and grayscale digital-to-analog conversion the resistor on the i set pin programs the nominal led current (10ma to 50ma) for all the channels. individual led channel can be adjusted to a different current setting by its own 6-bit dot correction register. the adjustable led current ranges from 0.5x to 1.5x of the nominal led current in 63 linear steps. see more details about setting nominal led current and dot correction in the applications information section. in addition to the dot correction current adjustment, individual led channels can also be modulated by their own grayscale pwm dimming signal. to achieve a better performance , all the grayscale pwm dimming signals are synchronized to the same frequency with no phase shift between rising edges . each constant current sink is enabled or disabled when its grayscale pwm dimming signal goes high or low. this periodic grayscale pwm dimming signal is generated by its own 12-bit grayscale register with a duty cycle from 0/4096 to 4095/4096 and a period equal to 4096 pwmck clock cycles. the generation of the grayscale pwm dimming signal is best understood by referring to figure 4. the lvds signals pwmck + , pwmck C are abbreviated to the pwmck signal. after en = 1 is set, the first rising edge of the pwmck signal will increase the internal 12-bit grayscale counter from zero to one and turn on all the led channels with grayscale value not zero. each following rising edge of the pwmck signal increases the grayscale counter by one. any led channel will be turned off when its 12-bit grayscale register value is equal to the value in the gray- scale counter. to generate a 100% duty cycle for all the grayscale pwm dimming signals, the pwmck signal can be paused before counting to the value in any individual 12-bit grayscale registers. setting en = 0 will reset the grayscale counter to zero and turn off all the led chan- nels immediately. dual-loop analog or control the switching frequency can be programmed from 200khz to 1mhz with the resistor connected to the rt pin and it can be synchronized to an external clock using the sync pin . each switching cycle starts with the gate driver turning on the external p-channel mosfet m1 and the inductor current is sampled through the sense resistor r s between the isp and isn pins. this current is amplified and added to a slope compensation ramp signal, and the resulting sum is fed into the positive terminal of the pwm compara- tor. when this voltage exceeds the level at the negative terminal of the pwm comparator, the gate driver turns off m1. the level at the negative terminal of the pwm comparator is set by either of two error amplifiers g m1 and g m2 . in this dual-loop analog or control, the fb loop g m1 regulates the fb pin voltage to 1.205v and the led loop g m2 regulates the minimum active led pin voltage (led00 to led15) to 0.7v. in the start-up phase, the g m2 is disabled and the output led bus voltage is regulated towards the feedback resistor programmed led bus volt- age. this fb programmed voltage defines the maximum www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 17 37451f led bus voltage and should be programmed high enough to supply the worst-case led string across temperature, current, and manufacturing variation. adaptive- tracking-plus-precharging higher system efficiency and faster transient re- sponse are two highly anticipated specifications in an individually-modulated multi-channel led driver chip. the lt 3745 -1 uses a patent pending adaptive -tracking - plus-precharging technique to achieve both of them simultaneously. besides 16 internal grayscale pwm dimming signals, the part also generates another internal precharging signal prechg. as shown in figure 4, the prechg signal divides any grayscale pwm dimming cycle into two phases: tracking phase when prechg = 0 and precharging phase when prechg = 1. during each grayscale pwm dimming cycle C 4096 pwmck clock cycles, the prechg signal stays low for the first 3584 clock cycles (7/8 of the grayscale pwm dimming period) and goes high for the rest 512 clock cycles (1/8 of the grayscale pwm dimming period). in the event of all the led channels being not active (i.e., either fault or off) before the 3585th pwmck clock, the prechg signal will go high immediately. to better explain the operation of the adaptive-tracking- plus-precharging technique, a simplified application system with 3-channel led array is presented in fig- ure 5. each channel consists of a single led with the forward voltage drop equal to 3.1v, 3.5v, and 3.9v, respectively. three internal grayscale pwm dimming signals pwm 1, pwm 2, and pwm 3 are used to modulate each led channel. at the beginning of each grayscale pwm dimming cycle, all three led channels are turned on and the tracking phase starts with prechg = 0. the amplifier g m2 is enabled and takes the control from the amplifier g m1 , regulating the minimum active led pin voltage to 0.7v. with the v led3 equal to 0.7v, the output led bus voltage is tracked to 4.6v. subsequently, at a certain time instant t 1 when the third channel is turned off, the minimum active led pin voltage goes to v led2 , 1.1v. then the amplifier g m 2 tracks the output led bus voltage operation figure 4. grayscale pwm dimming and precharging signal timing chart pwmck 4096 4095 1 2 3584 1 2 3 c1/en i(led00) reg = 0x002 reg = 0xfff tracking phase precharging phase reg = 0x000 i(led01) t wh-pwm t wl-pwm t pd-pwm i(led15) prechg 3585 37451 f04 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 18 37451f down to 4.2v to maintain the minimum active led pin voltage equal to 0.7v again. similarly, at the next time instant t 2 , the output led bus voltage is tracked down to 3.8 v. in this manner , the adaptive -tracking technique eliminates unnecessary power dissipation across the current sinks and yields superior system efficiency when compared to a constant 4.6v output voltage. at a later time instant t 3 when the prechg signal goes high, the amplifier g m2 is disabled and gives the control back to the amplifier g m1 . the amplifier gm1 regulates the output led bus voltage towards the fb programmed maximum value 4.6v to guarantee shorter minimum led on-time for the next grayscale pwm dimming operation cycle. without the precharging phase, the output led bus voltage will stay at 3.8v before the next grayscale pwm dimming cycle , when all the 3 led channels will be turned on again. at that time the 3.8v led bus voltage is too low to keep all the led channels in regulation, and the minimum led on-time is greatly increased to accommodate the slow transient response of the switch- ing buck converter charging the output capacitor from 3.8v to 4.6v. this adaptive-tracking- plus-precharging led bus voltage technique simultaneously lowers the power dissipation in the LT3745-1 and maintains a shorter minimum led on-time. figure 5. adaptive- tracking-plus-precharging led bus voltage technique pwm 1 pwm 2 pwm 3 prechg ideal v out LT3745-1 v out constant v out 4096*t pwmck 4.6v 4.6v 4.2v 3.8v t 1 t 2 t 3 t 4 4.6v 4.2v 3.8v 3.1v (1) v out = 4.6v 37451 f05 (2) (3) 1.5v 1.1v 0.7v ? ? ? + ? + ? + + ? + + 3.5v 3.9v www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 19 37451f applications information globally, the LT3745-1 converts a higher input voltage to a single lower led bus voltage (v out ) supplying 16 parallel led strings with the adaptive-tracking-plus-precharging technique. locally, the part regulates and modulates the current of each string to an independent dot correction and grayscale pwm dimming setting sent by lvds logic serial data interface . this application information section serves as a guideline of selecting external components (refer to the block diagram) and avoiding common pitfalls for the typical application. programming maximum v out the adaptive-tracking-plus-precharging technique regu- lates v out to its maximum value during the start-up and precharging phases, and adaptively lowers the voltage to keep the minimum active led pin voltage around 0.7v during the tracking phase. therefore, the maximum v out should be programmed high enough to keep all the led pin voltages higher than 0.8v to maintain led current regulation across temperature, current, and manufactur - ing variation. as a starting point, the maximum led bus voltage, v out(max) , can be calculated as: v out(max) = 0.8v + n ? v f(max) where n is the number of led per string and v f(max) is the maximum led forward voltage rated at the highest operating current and the lowest operating temperature. the v out(max) is programmed with a resistor divider between the output and the fb pin. the resistor values are calculated as: r fb2 = r fb1 v out(max) 1.210v ? 1 ? ? ? ? ? ? tolerance of the feedback resistors will add additional er - rors to the output voltage, so 1% resistor values should be used. the fb pin output bias current is typically 120na, so use of extremely high value feedback resistors could also cause bias current errors. a typical value for r fb1 is 10k. v in power input supply range the power input supply for the lt 3745 -1 can range from 6 v to 55v , covering a wide variety of industrial power supplies . another restriction on the minimum input voltage v in(min) is the 2.1v minimum dropout voltage between the v in and isn pins, and thus the v in(min) is calculated as: v in(min) = v out(max) + 2.1v choosing switching frequency selection of the switching frequency is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses and gate charge losses. however, lower frequency opera- tion requires larger inductor and capacitor values. another restriction on the switching frequency comes from the input and output voltage range caused by the minimum switch on and switch off-time. the highest switching frequency f sw(max) for a given application can be calculated as: f sw(max) = min d min t on(min) , 1C d max t off(min) ? ? ? ? ? ? ? ? where the minimum duty cycle d min and the maximum duty cycle d max are determined by: d min = v out(min) + v d v in(max) + v d and d max = v out(max) + v d v in(min) + v d t on( min) is the minimum switch on- time (~200 ns), t off( min) is the minimum switch off-time (~120ns), v out(min) is the minimum adaptive output voltage , v in ( max ) is the maximum input voltage, and v d is the catch diode forward voltage (~0.5v). the calculation of f sw(max) simplifies to: f sw(max) = min 5 ? v out(min) + v d v in(max) + v d , 8.33 ? v in(min) C v out(max) v in(min) + v d ? ? ? ? ? ? ? ? mhz www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 20 37451f applications information obviously , lower frequency operation accommodates both extremely high and low v out to v in ratios. besides these common considerations, the specific appli- cation also plays an important role in switching frequency choice. in a noise- sensitive system, the switching frequency is usually chosen to keep the switching noise out of a sensitive frequency band. switching frequency setting and synchronization the LT3745-1 uses a constant switching frequency that can be programmed from 200khz to 1mhz with a resistor from the rt pin to ground. table 2 shows r t values for common switching frequencies. table 2. switching frequency f sw vs r t value f sw (khz) r t * (k) 200 280 300 182 400 133 500 105 600 84.5 700 71.5 800 60.4 900 53.6 1000 46.4 * recommend 1% standard values synchronizing the LT3745-1 oscillator to an external fre- quency can be achieved using the sync pin. the square wave amplitude, compatible to ttl /cmos logic, should have valleys that are below 0.6v and peaks that are above 2.4v. the synchronization frequency also ranges from 200khz to 1mhz, in which the r t resistor should be cho- sen to set the internal switching frequency around 20% below the synchronization frequency . in the case of 200 khz synchronization frequency, r t = 348 k is recommended. it is also important to note that when the synchroniza- tion frequency is much higher than the r t programmed internal frequency, the internal slope compensation will be significantly reduced, which may trigger sub-harmonic oscillation at duty cycles greater than 50%. inductor current sense resistor r s and current limit the current sense resistor, r s , monitors the inductor current between the isp and isn pins, which are the in- puts to the internal current sense amplifier. the common mode input voltage of the current sense amplifier ranges from 0v to (v in C 2.1v) or 36v absolute maximum value, whichever is lower. the current sense amplifier not only provides current information to form the current mode control, but also a 44mv threshold. the 44mv threshold across the r s resistor imposes an accurate current limit to protect both p-channel mosfet m1 and catch diode d1, and also to prevent inductor current saturation. good kelvin sensing is required for accurate current limit. the r s resistor value can be determined by: i out(max) = i l(max) C ? i l 2 where the maximum inductor current i l(max) is set by: i l(max) = 44mv r s i out(max) is the maximum output load current, and ?i l is the inductor peak-to-peak ripple current. allowing ad- equate margin for ripple current and external component tolerances, r s can be estimated as: r s = 35mv i out(max) inductor selection the critical parameters for selection of an inductor are inductance value, dc or rms current, saturation current, and dcr resistance. for a given input and output voltage, the inductor value and switching frequency will determine the peak-to-peak ripple current, ?i l . the ?i l value usually ranges from 20% to 50% of the maximum output load current, i out(max) . lower values of ?i l require larger and more costly inductors; higher values of ?i l increase the peak currents and the inductor core loss. an inductor www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 21 37451f applications information current ripple of 30% to 40% offers a good compromise between inductor performance and inductor size and cost. however, for high duty cycle applications, a ?i l value of ~20% should be used to prevent sub-harmonic oscillation due to insufficient slope compensation. the largest inductor ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation: l v out + v d v in(max) + v d ? v in(max) C v out f sw ? ? i l the inductor dc or rms current rating must be greater than the maximum output load current i out(max) and its saturation current should be higher than the maximum inductor current i l(max) . to achieve high efficiency, the dcr resistance should be less than 0.1, and the core material should be intended for high frequency applications . power mosfet selection important parameters for the external p-channel mosfet m 1 include drain - to - source breakdown voltage ( v ( br ) dss ) , maximum continuous drain current (i d(max) ), maximum gate-to- source voltage (v gs(max) ), total gate charge (q g ), drain-to- source on resistance (r ds(on) ), reverse transfer capacitance (c rss ). the mosfet v (br)dss specification should exceed the maximum voltage across the source to the drain of the mosfet, which is v in(max) plus v d . the i d(max) should exceed the peak inductor current, i l(max) . since the gate driver circuit is supplied by the internal 6.8v v in referenced regulator, the v gs(max) rating should be at least 10v. each switching cycle the mosfet is switched off and on, a packet of gate charge q g is transferred from the v in pin to the gate pin , and then from the gate pin to the cap pin. the resulting dq g /dt is a current that must be supplied to the c cap capacitor by the internal regulator. the maximum 22ma current capability of the internal regulator limits the maximum q g(max) it can deliver to: q g (max) = 22ma f sw therefore, the q g at v gs = 6.8 v from the mosfet data sheet should be less than q g(max) . for maximum efficiency, both r ds(on) and c rss should be minimized. lower r ds(on) means less conduction loss while lower c rss reduces transition loss. unfortunately, r ds(on) is inversely related to c rss . thus balancing the conduction loss with the transition loss is a good criterion in selecting a mosfet. for applications with higher v in voltages (24v) a lower c rss is more important than a low r ds(on) . catch diode selection the catch diode d1 carries load current during the switch off- time. important parameters for the catch diode includes peak repetitive reverse voltage (v rrm ), forward voltage (v f ), and maximum average forward current (i f(av ) ). the diode v rrm specification should exceed the maximum reverse voltage across it, i.e., v in(max) . a fast switching schottky diode with lower v f should be used to yield lower power loss and higher efficiency. in continuous conduction mode, the average current conducted by the catch diode is calculated as: i d( avg ) = i out ? (1 C d) the worst-case condition for the diode is when v out is shorted to ground with maximum v in and maximum i out at present. in this case, the diode must safely conduct the maximum load current almost 100% of the time. to improve efficiency and to provide adequate margin for short- circuit operation, a schottky diode rated to at least the maximum output current is recommended. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 22 37451f applications information c in , c vcc , and c cap capacitor selection a local input bypass capacitor c in is required for buck converters because the input current is pulsed with fast rise and fall times. the input capacitor selection criteria are based on the voltage rating, bulk capacitance, and rms current capability. the capacitor voltage rating must be greater than v in( max ) . the bulk capacitance determines the input supply ripple voltage and the rms current capability is used to keep from overheating the capacitor. the bulk capacitance is calculated based on maximum input ripple, ?v in : c in = d max ? i out(max) ? v in ? f sw ?v in is typically chosen at a level acceptable to the user. 100mv is a good starting point. for ceramic capacitors, only x5r or x7r type should be used because they retain their capacitance over wider voltage and temperature ranges than other types such as y5v or z5u. aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area . the capacitor rms current is: i cin (rms) = i out ? v out ? ( v in C v out ) v in 2 if applicable , calculate at the worst- case condition , v in = 2 ? v out . the capacitor rms current rating specified by the manufacturer should exceed the calculated i cin ( rms ) . due to their low esr, ceramic capacitors are a good choice for high voltage, high rms current handling. note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. for a larger high voltage capacitor value, the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach. multiple capacitors may also be paralleled to meet size or height requirements in the design. locate the capacitor very close to the mosfet switch and the catch diode, and use short, wide pcb traces to minimize parasitic inductance. the general discussion above also applies to the capacitor c vcc at the v cc pin and the capacitor c cap between the v in and cap pins. typically , a 10f 10v-rated ceramic capaci- tor for c vcc and a 0.47f 16v-rated ceramic capacitor for c cap should be sufficient. c out capacitor selection the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the LT3745-1 to produce the dc output containing a con- trolled voltage ripple. it also stores energy to satisfy load transients and to stabilize the dual-loop operation. thus the selection criteria for c out are based on the voltage rating, the equivalent series resistance esr, and the bulk capacitance. as always, choose the c out with a voltage rating greater than v out(max) . the LT3745-1 utilizes the output as the dominant pole to stabilize the dual loop operation, so the c out value determines the unity gain frequency f ugf , which is set around 1/10 of the switching frequency. to stabilize the fb loop during the start-up and precharging phases and the led loop during the tracking phase, a low esr capacitor (tens of m) should be used and its minimum c out is calculated as: c out = max 0.25 r s ? f ugf , 1.5 v out(max) ? r s ? f ugf ? ? ? ? ? ? ? ? the adaptive-tracking-plus-precharging technique moves the v out with the grayscale pwm dimming frequency to improve system efficiency, choosing a ceramic capacitor as the c out inevitably generates acoustic noise due to the piezo effect of the ceramic material. in an acoustic noise sensitive application, low esr tantalum or aluminum capacitors are preferred. when choosing a capacitor, www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 23 37451f look carefully through the data sheet to find out what the actual capacitance is under operating conditions (applied voltage and temperature). a physically larger capacitor, or one with a higher voltage rating, may be required. undervoltage lockout (uvlo) and shutdown LT3745-1 has three uvlo thresholds with hysteresis for the en/uvlo, v cc , and cap pins. the part will remain in uvlo mode not switching until all the en/uvlo, v cc , and (v in C v cap ) voltages pass their respective typical thresh- olds (1.30v, 2.86v, and 4.9v). as shown in figure 6, the en/uvlo pin can be controlled in two different ways. the en/uvlo pin can accept a digital input signal to enable or disable the chip. tie to 0.35v or lower to shut down the chip or tie to 1.34v or higher for normal operation. this pin can also be connected to a resistor divider between v in and ground to program a power input v in uvlo threshold. after r uv1 is selected, r uv2 can be calculated by: r uv2 = r uv1 ? v in(on) 1.3v C 1 ? ? ? ? ? ? where v in(on) is the power input voltage above which the part goes into normal operation. it is important to check the en/uvlo pin voltage not to exceed its 4v absolute maximum rating: v in(max) ? r uv1 r uv1 + r uv2 < 4v applications information soft-start during soft-start, the ss pin voltage smoothly ramps up inductor current and output voltage. the effective voltage range of ss pin is from 0v to 1v. therefore, the typical soft-start period is: t ss = c ss ? 1v 12a where c ss is the capacitor connected at ss pin and 12a is the soft-start charge current. whenever a uvlo or thermal shutdown occurs, the ss pin will be discharged and the part will stop switching until the uvlo event has disappeared and the ss pin has reached it reset threshold, 0.35v. the part then initiates a new soft-start cycle. setting nominal led current the nominal led current is defined as the average led current across 16-channel when all the individual dot cor - rection registers are set to 0x20. the nominal led current is programmed by a single resistor, r iset , between the i set pin and ground. the voltage at the i set pin, v iset , is trimmed to an accurate 1.205v, generating a current inversely proportional to r iset . the nominal led current, i led(nom) , can be calculated as: i led (nom) = v iset r iset ? 2500 figure 6. methods of controlling the en/uvlo pin v in v cc en/uvlo from controller (6a) (6b) 37451 f06 v in v cc en/uvlo v in r uv2 r uv1 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 24 37451f i led(nom) must be set between 10ma and 50ma. typical r iset resistor values for various nominal led currents are listed in table 3. table 3. nominal led current i led(nom) vs. r iset value i led(nom) (ma) r iset * (k) 10 301 20 150 30 100 40 75 50 60.4 * recommend 1% standard values setting dot correction the LT3745-1 can adjust the led current for each channel independently. this fine current adjustment, also called dot correction, is mainly used to calibrate the brightness deviation between led channels. the 6-bit (64 steps) dot correction setting adjusts each led current from 0.5x to 1.5x of the nominal led current according to: i ledn = i led(nom) ? dc n + 32 64 ? ? ? ? ? ? where i ledn is the nth led current and dc n is the nth programmed dot correction setting (dc n = 0 to 63). the fine current step over the nominal led current gives an excellent resolution: ? i led i led (non) = 1 64 1.56% which enhances the relative led current match accuracy if used as calibration. setting grayscale although adjusting the led current changes its luminous intensity, or brightness, it will also affect the color match- ing between led channels by shifting the chromaticity coordinate. the best way to adjust the brightness is to control the amount of led on-/off-time by pulse width modulation ( pwm ). the LT3745-1 can adjust the brightness for each channel independently . the 12- bit grayscale pwm dimming results in 4096 linear brightness steps from 0% to 99.98%. the brightness level gs n % for channel n can be calculated as: gs n % = gs n 4096 ? 100% where gs n is the nth programmed grayscale setting (gs n = 0 to 4095). open/short led fault the LT3745-1 has individual led fault diagnostic circuitry that detects both open and short led faults for each chan- nel. the open led fault is defined as any led string is open or disconnected from the circuit ; and the short led fault is defined as any led string is shorted across itself. the open led flag is set if the led pin voltage is lower than 0.35v (typical) during on status with initial 500ns blanking. the short led flag is set if the led pin voltage is higher than 75% of the led bus voltage v out any time. if one led channel is shorted across itself, the channel will be turned off to eliminate unnecessary power dissipation. the function can also be used to disable led channels by connecting their led pins to the output directly. both the open and short led flags are combined to set the led fault bits (s0 to s15) in the status frame to 1. thermal protection the LT3745-1 has two overtemperature thresholds: one is the fixed internal thermal shutdown and the other one is programmed by a resistor, r tset , between the t set pin and ground. when the junction temperature exceeds 165c, the part will enter thermal shutdown mode, shut down serial data interface , turn off led channels, and stop switching. after the junction temperature drops below 155c, the part will initiate a new soft-start. applications information www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 25 37451f when the r tset is placed at the t set pin, a current equal to the current flowing through the r iset passes the r tset , generating a voltage v tset at the t set pin, which is calculated as: v tset = 1.205v ? r tset r iset then the v tset is compared to an internal proportional- to-absolute-temperature voltage v ptat , v ptat = 1.72mv ? (t j + 273.15) where t j is the LT3745-1 junction temperature in c. when v ptat is higher than v tset , an overtemperature flag ot = 1 is set. once the r tset programmed temperature is exceeded, the part will also gradually derate the nominal led current i led(nom) to limit the total power dissipation without interrupting its normal operation. cascading devices and determining serial data interface clock in a large lcd backlighting or led display system , multiple LT3745-1 chips can be easily cascaded to drive all the led strings . the minimum serial data interface clock frequency f scki for a large display system can be calculated as: f scki = n LT3745-1 ? 194 ? f refresh applications information where n LT3745-1 is the number of LT3745-1 chips and f refresh is the refresh rate of the whole system. calculating power dissipation the total power dissipation inside the chip can be calcu- lated as: p total = v in ? (i vin + f sw ? q g ) + v cc ? i vcc + gs n % ? i ledn ? v ledn n = 0 15 where i vin is the power input v in quiescent current, i vcc is the v cc supply current, and v ledn is the led pin volt- age for channel n. from the total power dissipation p total , the junction temperature t j can be calculated as: t j = t a + p total ? ja keep t j below the maximum operating junction tempera- ture 125c. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 26 37451f typical application figure 7. 16-channel led driver, 500khz buck, 1 led 25ma to 75ma per channel, 100hz 12-bit dimming en/uvlo sync rt ss v cc i set t set scki + scki ? sdi + sdi ? ldi scko + scko ? sdo + sdo ? led10 led11 led12 led13 led14 led15 led00 led01 led02 led03 led04 led05 . . . . . . LT3745-1 100k v in 10v to 40v en v cc 3v to 3.6v v in cap 0.47f 16v m1 d1 gate gnd fb isp isn 4.7f 50v 23.2k 10k c1 220f l1 22h 25m 4v maximum output voltage pwmck + lvds c1: sanyo 6tpe220mi d1: diodes dfls160 l1: wrth electronik 7447779122 m1: vishay si9407bdy 409.6khz lvds clock lvds pwmck ? 37451 f07 10f 10v 105k 10nf 60.4k 32.4k www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 27 37451f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3745-1 28 37451f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0512 ? printed in usa related parts typical application part number description comments lt3745 16-channel 50ma led driver with buck controller v in : 6v to 55v, v out(max) = 36v, 6-bit dot correction current adjustment, 12-bit grayscale dimming, 6mm 6mm qfn package lt3746 32-channel 20ma led driver with buck controller v in : 6v to 55v, v out(max) = 13v, 6-bit dot correction current adjustment, 12-bit grayscale dimming, 5mm 9mm qfn package lt3476 quad output 1.5a, 2mhz high current led driver with 1,000:1 dimming v in : 2.8v to 16v, v out(max) = 36v, true color pwm ? dimming = 1000:1, i sd < 10a, 5mm 7mm qfn-10 package lt3486 dual 1.3a , 2mhz high current led driver v in : 2.5v to 24v, v out(max) = 36v, true color pwm dimming = 1000:1, i sd < 1a, 5mm 3mm dfn-16 tssop-16e package lt3496 triple output 750ma, 2.1 mhz high current led driver with 3,000:1 dimming v in : 3v to 30v, v out(max) = 60v, true color pwm dimming = 3000:1, i sd < 1a, 4mm 5mm qfn-28 package lt3595 45v, 2.5mhz 16-channel full featured led driver v in : 4.5v to 45v, v out(max) = 45v, true color pwm dimming = 5000:1, i sd < 1a, 5mm 9mm qfn-56 package lt3598 44v, 1.5a, 2.5mhz boost 6-channel 30ma led driver v in : 3v to 40v, v out(max) = 44v, true color pwm dimming = 1000:1, i sd < 1a, 4mm 4mm qfn-24 package lt3599 44v, 2a, 2.5mhz boost 4-channel 120ma led driver v in : 3v to 40v, v out(max) = 44v, true color pwm dimming = 1000:1, i sd < 1a, 4mm 4mm qfn-24 package lt3754 60v, 1mhz boost 16-channel 50ma led driver with true color 3,000:1 pwm dimming and 2.8% current matching v in : 4.5v to 40v, v out(max) = 60v, true color pwm dimming = 3000:1, i sd < 1a, 5mm 5mm qfn-32 package lt3760 60v, 1mhz boost 8-channel 100ma led driver with true color 3,000:1 pwm dimming and 2.8% current matching v in : 4.5v to 40v, v out(max) = 60v, true color pwm dimming = 3000:1, i sd < 1a, tssop-28e package figure 8. 16-channel led driver, 1mhz buck, 10 leds, 25ma to 75ma per channel, 500hz 12-bit dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . en/uvlo sync rt ss v cc i set t set led13 led14 led15 led00 led01 led02 . . . . . . LT3745-1 100k v in 42v to 55v en v cc 3v to 3.6v v in cap 0.47f 16v gate gnd fb isp isn 4.7f 100v 267k 10k c1 47f 2 l1 47h m1 d1 25m 33.4v maximum output voltage pwmck + pwmck ? 2.048mhz lvds clock 37451 f08 10f 10v 46.4k 10nf 60.4k 32.4k c1: sanyo 35svpd47m d1: diodes dfls160 l1: wrth electronik 744771147 m1: vishay si9407bdy scki + scki ? sdi + sdi ? ldi scko + scko ? sdo + sdo ? lvds lvds www.datasheet.co.kr datasheet pdf - http://www..net/

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